(a) Field of the Invention
The present invention relates to a thin film transistor array panel for a liquid crystal display and a method of manufacturing the same.
(b) Description of the Related Art
Liquid crystal display (LCDs) are one of the most widely used flat panel display (FPD) configurations. The liquid crystal display has two panels having electrodes for generating an electric field and a liquid crystal layer interposed between the two panels. The transmittance of incident light is controlled by the intensity of the electric field applied to the liquid crystal layer.
The typical liquid crystal display uses a thin film transistor as a switching element. Data lines and gate lines, which cross each other to define pixels in a matrix array, are formed on the panel on which the thin film transistors are disposed. Further, a pixel electrode is formed in each pixel.
However, in the process of manufacturing the panels for the liquid crystal display, if a conductive material remains on an unintended portion of the panel, in particular between adjacent pixel electrodes or between the pixel electrodes and the data lines, a pixel defect occurs in which the pixels remain in a white state even when the same are controlled to an OFF state. This is a result of shorting of the pixel electrodes with the data lines or adjacent pixel electrodes.
Also, during the operation of the liquid crystal display, after a pixel electrode receives an image signal, which is transmitted via a corresponding data line, through the thin film transistor within the same pixel as the pixel electrode, the pixel: electrode is then floated before receiving a subsequent image signal. However, the data line continuously transmits image signals to other pixel columns. Accordingly, a voltage of the image signals distorts a potential of the pixel electrode which is in a floating state. This results in an overall reduction in picture quality of the LCD. Such a problem worsens with increases in a coupling capacitance generated between the data lines and the pixel electrodes.
Furthermore, in the LCD panel manufacturing process, because the pixel electrodes and the data lines are formed through different photolithography processes, if there occurs mask misalignment, the coupling capacitance between the pixel electrodes and the data lines is varied. In particular, in case of using a stepper as an exposure device to conduct exposure in units of blocks, the degree of misalignment is different between the blocks such that stitches are generated, resulting in a difference of brightness between the blocks. This stitch defect is particularly severe in column or dot inversions drive type LCDs.
It is an object of the present invention to reduce pixel defects by preventing shorts between pixel electrodes and data lines by performing a conductive reaming process in a LCD manufacturing process.
It is another object of the present invention to minimize misalignment generated in the LCD manufacturing process.
These and other objects are provided, according to the present invention, by forming an opening at a circumference of a pixel electrode, or an align pattern on both sides of a data line when forming the data line.
According to the present invention, a gate wire including a gate line, and gate electrodes connected to the gate line are formed in the horizontal direction on a insulating substrate. A gate insulating layer covers the gate wire, and a semiconductor pattern made of semiconductor is formed on the gate insulating layer of the gate electrode. A data wire including a data line defining a pixel by intersecting the gate line, and a source electrode and a drain electrode formed on the semiconductor pattern and separated from each other on the gate electrode are formed in the vertical direction on the gate insulating layer. A passivation layer covering the data wire has a contact hole exposing the drain electrode and an opening at the circumference of the pixel. The pixel electrode connected to the drain electrode through the contact hole is formed in the pixel on the passivation layer.
Here, the opening may be extended into the gate insulating layer, and it is possible that the gate line has a first gate line and a second gate line, and a gate connecting portion interconnecting the first and second gate lines.
In another embodiment according to the present invention, the pixel electrode may be directly located on/under the data wire. Here, it is preferable that the opening is formed when etching the gate insulating layer to form the contact hole exposing a gate pad connected to the gate line, and a wet etch process is executed to remove a remaining conductive material such as indium tin oxide (ITO) for the pixel electrode. On the other hand, the remaining conductive material for the pixel electrode may be removed before etching the gate insulating layer.
Furthermore, in another embodiment according to the present invention, a gate line is formed in the horizontal direction on the insulating substrate, and a gate insulating layer covers the gate line. A semiconductor pattern is formed on the gate insulating layer. Formed on the gate insulating layer are a data wife including a data line formed in the vertical direction, a source electrode connected to the data line on the semiconductor pattern, and a drain electrode opposite the source electrode with respect to the gate electrode formed on the semiconductor pattern; and an align pattern located at both sides of the data line are formed on the gate insulating layer. A passivation layer covers the data line, the align pattern, the drain electrode, and the source electrode, and has a contact hole exposing the drain electrode. A pixel electrode is formed on the passivation layer and connected to the drain electrode through the contact hole.
Furthermore, in another embodiment according to the present invention, a gate line is formed in the horizontal direction on the insulating substrate, and a gate insulating layer covers the gate line. A semiconductor pattern is formed on the gate insulating layer. Formed on the gate insulating layer are a data wire including a data line formed in the vertical direction, a source electrode connected to the data line on the semiconductor pattern, and a drain electrode opposite the source with respective to the gate electrode formed on the semiconductor pattern; and an align pattern located on both sides of the data line. A pixel electrode overlapping and connected to the drain electrode and the align pattern is also formed on the gate insulating layer. A passivation layer is formed on the pixel electrode.
At this time, ohmic contact layers may be formed between the source electrode and the semiconductor pattern, and between the drain electrode and the semiconductor pattern, and the passivation layer and the gate insulating layer may have an opening exposing the insulating substrate between the align pattern and the data line.
In a manufacturing method of a thin film transistor array panel for a liquid crystal display according to the present invention, a gate line is formed on an insulating substrate, and a gate insulating layer and a semiconductor layer are deposited thereon. The semiconductor layer is patterned to form a semiconductor patter. A data wire including a data line, a source electrode and a drain electrode, and an align pattern are formed on the gate insulating layer. A passivation layer is deposited and patterned to form a contact hole exposing the drain electrode and an opening between the data line and the align pattern, and a pixel electrode is formed.
In another manufacturing method of a thin film transistor array panel for a liquid crystal display according to the present Invention, a gate line is formed on an insulating substrate, and a gate insulating layer and a semiconductor layer are deposited thereon. The semiconductor layer is patterned to form a semiconductor pattern A a data wire including a data line a source electrode and a drain electrode, and a align pattern are formed on the gate insulating layer. A pixel electrode connected to the drain electrode is formed on the gate insulating layer. A passivation layer is deposited and patterned to form an opening between the data line and the align pattern. Here, the step of etching the data line and the align pattern, which are exposed through the opening, may be added.
Furthermore, in another embodiment according to the present invention, a gate wire including a gate line extended in the horizontal direction, and a gate electrode connected to the gate line is formed on an insulating layer. A gate insulating layer covers the gate wire, and a semiconductor pattern is formed on the gate insulating layer. A data wire including a data line extended in the vertical direction, a source electrode, and a drain electrode separated from the source electrode and opposite the source electrode with respect to the gate electrode is formed on the semiconductor pattern. An align pattern located on both sides of the data line is formed on the semiconductor pattern, and a passivation layer pattern having a contact hole exposing the drain electrode and an opening between the data line and the align pattern covers the data wire and the align pattern. A pixel electrode connected to the drain electrode via the contact hole is formed opposite the drain electrode with respect to the passivation layer.
At this time, it is preferable that portions of the pixel electrode and the align pattern overlapping each other, and a distance between the data line and a boundary of the pixel electrode adjacent to the data line is equal to or greater than a distance between the data line and a boundary of the align pattern adjacent to the data line. A portion of the align pattern may be exposed through the opening, and the pixel electrode may be extended on the align pattern and connected to the align pattern. The opening may be extended to the semiconductor pattern and the gate insulating layer, and the insulating substrate may be exposed through the opening. It is preferable that the semiconductor pattern and the gate insulating layer are under-cut under the align pattern adjacent to the data line.
Repair lines overlapping a portion of the data line and both end portions of the align patterns may be added on the same layer as the gate wire. A supplementary data line of which both end portions are connected to the data line, intersecting the gate line, may be formed on the same layer as the data wire. A supplementary data line of which the both end portions overlap the data line, intersecting the gate line, may is formed on the same layer as the pixel electrode.